TAD PGS, Inc. a un travail pour vous.

 

Détails du poste


Engineering


Senior FPGA Design Engineer  Camden, NJ  : 2/23/2026
Description fonction

Offre d'emploi nº:

215701

Catégorie Offre Emploi:

Engineering

Type de position:

Associate - W2

Durée:

12 months


We have an outstanding Contract position for a Senior FPGA Design Engineer to join a leading Company located in the Camden, NJ surrounding area.

Pay Rate: $90 - $115
**US Citizenship is required.**
**Candidate must possess an Active Secret Security Clearance.**

Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key design teamresponsible for the delivery of FPGAs for defense applications. Candidates will architect and implement FPGA design, with hands-on design/debug with primarily Ethernet,  I2C, SPI, AXI protocols.

Responsibilities:
  • Derive FPGA design specifications from system requirements
  • Develop a detailed FPGA architecture for implementation
  • Implement design in RTL (VHDL) and perform module-level simulations
  • Perform Synthesis, Place and Route (PAR), and Static Timing Analysis (STA)
  • Perform RTL quality using: Lint, Reset Domain Crossing (RDC), Clock Domain Crossing (CDC), Static Formal EDA
  • Generate verification test plans and perform end-to-end simulations
  • Support Board, FPGA bring up
  • Validate design through HW/SW integration test with test equipment
  • Support product collateral for NSA certification
 
Basic Hiring Criteria:
  • Bachelor of Science (BS) four-year degree, Master's (MS), or PhD from an accredited course of study in engineering, engineering technology (chemistry, physics, mathematics, data science, or Electrical/Electronics/Computer Engineering/Computer Science)
  • Minimum 3-5 years of experience designing FPGA products with VHDL
  • Active DoD Security Clearance
  • Experience with Xilinx FPGAs and Vivado
  • Experience with a revision control system
  • Experience with Earned Value Management (EVM)
  • Good written, verbal, and presentation skills
 
Desired Qualifications:
  • Experience with mapping algorithms to architecture
  • Experience in C++ (OOP)
  • Experience with any of these protocols: Ethernet, TCP/IP, PCIe, NVMe, USB
  • Experience with Xilinx SoC design with SDKs and PetaLinux OS
  • Experience with High-Level Synthesis (HLS) with Vivado HLX or Mentor Catapult

Benefits offered to vary by the contract. Depending on your temporary assignment, benefits may include direct deposit, free career counseling services, 401(k), select paid holidays, short-term disability insurance, skills training, employee referral bonus, affordable medical coverage plan, and DailyPay (in some locations). For a full description of benefits available to you, be sure to talk with your recruiter.

 
Aptitudes Requises

Autorisation minimale de sécurité:

Secret

 

Military connected talent encouraged to apply.

VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled 

To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit http://www.tadpgs.com/candidate-privacy/ or https://pdsdefense.com/candidate-privacy/

The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:

  • The California Fair Chance Act
  • Los Angeles City Fair Chance Ordinance
  • Los Angeles County Fair Chance Ordinance for Employers
  • San Francisco Fair Chance Ordinance




 

Vous avez déjà un compte? Connectez-vous ici